Field of the Invention
This invention relates generally to bus interfaces, and, more particularly, to address range decomposition, e.g., for a Peripheral Component Interconnect Express (PCIe) Bus, and a smart bridge implementation thereof.
Description of the Related Art
PCI Express (Peripheral Component Interconnect Express, also abbreviated as PCIe), is a high-speed serial computer expansion bus standard offering numerous improvements over the older PCI, PCI-X, and AGP (Accelerated Graphics Port) bus standards. These improvements include higher maximum system bus throughput, lower I/O pin count and a smaller physical footprint, better performance-scaling for bus devices, more detailed error detection and reporting mechanism, and native hot-plug functionality. Conceptually, the PCIe bus is a high-speed serial interconnect bus using shared address/data lines. Accordingly, the PCIe bus differs from the older PCI bus in its bus topology. While PCI uses a shared parallel bus architecture, where the PCI host and all devices share a common set of address/data/control lines, the PCIe bus is based on a point-to-point topology, with separate serial links connecting every device to the root complex (or host). Because of this shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to one master at a time, in a single direction.
As mentioned above, PCIe devices communicate via a logical connection referred to as an interconnect or a link, which provides a point-to-point communication channel between two PCIe ports, allowing both ports to send/receive PCI-requests (such as configuration read/write, I/O read/write, memory read/write) and interrupts. In a system that uses PCI or PCIe bus, in order for a PCI device to be addressable, the device must first be mapped into the I/O port address space or the memory-mapped address space of the system. The system's firmware/device drivers or the operating system typically program the Base Address Registers (referred to as BARs) to inform the device of its address mapping by writing configuration commands to the PCI controller.
The PCIe eXtensions for Instrumentation (PXI Express)—introduced in 2005 by National Instruments—is one of several electronic instrumentation platforms in current use, and represents a modular instrumentation platform that leverages existing technology to deliver high performance and low cost modular instrumentation. PXI Express is ideally suited for building electronic test-equipment and/or automation systems, and complements the industry standard PCIe with extra features to facilitate electronic testing and data acquisition. PXI Express affords great flexibility in building test equipment and/or automation systems to exact requirements, often fitted with custom software for managing the entire system.
PXI Express was conceived for measurement and automation applications that typically require high-performance and a rugged industrial form-factor. PXI Express also allows for module selection from a large number of vendors, with the modules easily integrating into a single PXI Express system. Overall, PXI Express uses PC-based technology as part of an industry standard governed by the PXI Systems Alliance (PXISA), ensuring standards compliance and system interoperability. PXI Express modules are available for a wide variety of test, measurement, and automation applications, from switching modules to high performance microwave vector signal generation and analysis instruments.
PXI Express modules are typically designed to implement specific functions, such as analog signal capture, RF signal analysis, and/or waveform generation. PXI Express modules that provide instrument functions usually plug into a PXI Express chassis that may include its own controller running an industry standard Operating System (e.g. Windows XP, Windows 2000, and/or Linux), or a PCI Express-to-PXI Express bridge that provides a high-speed link to a desktop PC controller. Similarly, multiple PXI Express racks may be linked together with PCI Express bridges (or bridge cards) to build very large systems such as multiple source microwave signal generator test stands for complex ATE applications.
PCI devices have two ways to specify resources, base address registers (BARs) and forwarding address ranges (which may also be referred to as “forwarding ranges”). BARs have a relatively modest minimum size but both size and alignment are restricted to powers of two. PCI endpoints have only BARs to describe resource requirements.
When bridges were added to the PCI specification, forwarding address ranges were needed. BAR allocation restrictions would not work for forwarding ranges and so a new set of rules was created. In PCI, forwarding ranges have a minimum size of 1 MB (4 KB for IO) but no other alignment or size restrictions. Resources have the combined restrictions of the BAR(s) involved plus the combination of forwarding ranges those BARs are behind. This was not a problem originally because there were relatively few bridges with many BARs behind each bridge. With PCI Express, the most common case will typically have a single device with one BAR, or a small number of BARs, behind a bridge. This effectively imposes a 1 MB lower size bound on each BAR in the system.
In some current and near-future bus protocols, e.g., a next-generation MXI bus (Multisystem eXtension Interface Bus), also referred to as MXIbus, which is a high performance communication link for interconnecting devices, e.g., a GPIB card and a VXI cage, there are circumstances where bridge forwarding ranges may be required to be represented as BARs. A forwarding range will always be large but the BAR representation also imposes a power of two limit on both size and alignment. This can cause rapid acceleration of resource requirements due to fragmentation loss.
For example, consider a forwarding range of 3 MB that exists because it is forwarding three subordinate bridges which themselves are forwarding one BAR each. When the 3 MB range is represented as a BAR, it will be expanded to 4 MB in order to be represented as a power of two, which represents a ⅓ (˜33%) increase in wasted allocation.
Accordingly, improved systems and methods for managing address allocations are desired.